The present invention relates generally to digital phase-locked loops, and more specifically to analog phase error correction circuits for high speed frequency synthesizers used in digital phase-locked loops.
Digital phase-locked loops (DPLLs) are used in a wide array of applications. A specific example is the use of DPLLs to generate pixel clocks in video applications. These clock signals synchronize data displayed on flat panel displays such as liquid crystal displays (LCD), and other types of monitors, as well as LCD and plasma televisions, projectors, and other types of display apparatus. A DPLL in this type of application typically receives a horizontal synchronizing signal (HSYNC) and a divide ratio, and divides the HSYNC signal period by the divide ratio to generate a pixel clock.
DPLLs include a numerically controlled oscillator (NCO), which may be used to generate the pixel clock. An NCO receives a clock signal and phase increment information, and accumulates the phase increment information each clock signal. The accumulated phase information can be used to find an entry in a look-up table, the entries of which typically correspond to a sinewave. The look-up table provides an output each NCO clock cycle. These outputs form a digitized sinewave, the frequency of which depends on phase increment information. This sinewave can then be filtered and used as a pixel clock.
The accumulated phase information includes an overflow and a remainder signal. This overflow signal is typically a one bit signal that may alternately be used as the pixel clock. The overflow signal has a frequency that also depends on the phase increment information. Pixel clocks generated this way have an associated jitter of one NCO clock cycle period caused by a phase error that accumulates over a number of pixel clock cycles. Thus, additional circuitry for adjusting the phase of the overflow signal is needed to reduce this phase error.
Unfortunately, conventional methods of making this adjustment are either not very accurate or often multiplex multiple clock lines that cause high switching noise and consume a large amount of power and die area. Thus what is needed are circuits, methods, and apparatus that reduce or remove this phase error in such a way that the synthesized pixel clock has high accuracy and low jitter and noise.